The present invention generally relates to semiconductor device manufacturing, and more particularly to fabricating an air gap with a barrier layer.
A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wiring. In very large scale integration (VLSI) chips, these metal patterns are multilayered and are separated by layers of an insulating material. Typical integrated circuit chip designs utilize one or more wiring levels. Insulating or dielectric materials are employed between the wires in each level (intra-level dielectric) and between the wiring levels (inter-level dielectric). The desire for smaller chips may result in higher device density and tighter space between wires and wire levels.